Keeping pace with the development of semiconductors, efforts to integrate more elements onto one semiconductor chip in high degree have been actively progressing. Particularly, in DRAM(Dynamic Random Access Memory) cell, various cell structures have been proposed to minimize the size of a element.
For high integration, it is preferable that a memory cell is composed of one transistor and one capacitor in a view to minimize the occupied area on a chip.
In a memory cell composed of one transistor and one capacitor as mentioned before, a signal charge is stored in a storage node of a capacitor which is connected to a transistor (switching transistor). Consequently, if the size of a memory cell is decreased for high integration of a semiconductor, because the size of the capacitor has to be decreased accordingly, the number of charges which can be stored in a storage node have to also decrease.
Therefore, in order to transmit a desired signal without any malfunction, the capacitor storage node of a memory cell has to have a surface area greater than a certain predetermined value to secure a capacitor capacity required for the transmission of a signal.
Thus, a capacitor storage node has to have a relatively large area within the limited area of a semiconductor substrate to decrease the size of a memory cell.
Of the various memory cell constructions proposed to increase the surface area of a capacitor storage node, a stack capacitor is a capacitor structure having the advantages of being favorable for high integration while being influenced by soft error little.
Further, a memory cell having stacked capacitor also has the advantages of being suitable for mass production with a relatively simple process.
Referring to FIGS. 1(a) to 1(g), one of stacked capacitor disclosed by H. Ogawa et al. (U.S. Pat No. 5,164,337) to increase capacitor capacity is explained hereinafter.
At first, as shown in FIG. 1(a), form a switching transistor 50 having N-impurity regions 19 functioning as a source and a drain, and gate poles 2, on a P-silicon substrate, then form a multi-layer insulation film of first oxide film 3, nitride film 4 and second oxide film 5 being coated successively on all over the surface of the formed switching transistor 50.
Next, as shown in FIG. 1(b), after forming contact hole 18 with a photo etching process for connecting the switching transistor with the capacitor storage node formed in the successive process, form first conduction layer 6 on all over the surface of the second oxide film 5 including the contact holes 18.
Thereafter, as shown in FIG. 1(c), form a multi-layer film 80 by depositions of more than two layers of insulation film (a first NSG (Nondoped Silicate Glass) film) 7, PSG (Phospho-Silicate Glass) film 8 and a second NSG film 9) having different wet etching property alternatively. Then form a desired pattern by first etching of the multi-layer film 80 with anisotropic etching in the first time.
Next, as shown in FIG. 1(d), etch the patterned multi-layer film 80 in NH4:HF=20:1 solution for two minutes with isotropic etching in the second time so as to form indented part thereon according to the difference of degree of etching of the multi-layer film 80.
Then, after forming a second conduction layer 10 on all over the surface of above resultant as shown in FIG. 1(e), etch back with anisotropic etching so as to leave the second conduction layer 10 only on the side of the multi-layer film 7, 8 and 9, and the first conduction layer 6 exposed thereafter as shown in FIG. 1(f).
And, by removing the multi-layer film 7, 8 and 9, and the second oxide film. 5 under the first conduction layer 6 with wet etching, a capacitor storage node 1 composed of first conduction layer 6 and the second conduction layer 10 can be completed.
Thereafter, by forming dielectric film and plate pole (not shown) using general capacitor forming process, a box shape semiconductor memory cell capacitor can be completed.
In the prior art technology described above, the indented parts are formed with wet etching, in the multi-layer film utilizing the difference of etching speed of the multi-layer film which has a problem that a precise control of the amount of etching is difficult on wet etching, and because the more the storage node is stacked, the weaker the mechanical strength of the column formed of the first conduction layer in the contact hole 18 to connect the switching transistor with the capacitor storage node becomes, the problem of low reliability arises.